An embedded memory typically refers to an integrated on-chip memory that supports a logic core. Embedding a memory on a processor increases a bus width and an operation speed. High-performance embedded memory is a key component in a data processing system because of high-speed and wide bus-width capability, which eliminates inter-chip communication.
Generally, a memory array has a plurality of bitcells. A bitcell refers to a part of an integrated circuit in which a single hit is stored. A typical 1T-1R bitcell consists of a transistor connected to a memory element. The transistor provides an access to the memory element that stores a bit. Typically, the transistor is connected to the memory element to change a state of the memory element from one value to another value to store a bit. A conventional embedded memory technology is a silicon-based technology which is not stackable and therefore low density.
FIG. 1 illustrates a side view of a conventional 1T-1R memory array 100. A transistor array 102 is deposited on a silicon wafer 101. Transistor array 102 consists of a plurality of transistors, such as a transistor 109 and a transistor 119 formed directly on silicon wafer 101. Metal layers 104, 105, and 106 separated by dielectric layers 103, 111, and 112 are formed above the transistor array 102. The metal layers 104, 105, 106, and 108 are connected through vias, such as vias 113, 114, and 115, as shown in FIG. 1. A memory element array 107 is on metal layer 106. Memory element array 107 consists of memory elements, such as a resistor memory element 116 and a resistor memory element 118. A metal layer 108 is formed on memory element array 107, as shown in FIG. 1.
Conventional 1T-1R memory array 100 consists of a plurality of bitcells, such as a bitcell 117 and a bitcell 121. Each transistor of the transistor array 102 is connected to a corresponding one memory element of the memory element array 107 to form bitcells. Bitcell 117 consists of transistor 109 connected to resistor memory element 116 by vias 113, 114, and 115. Bitcell 121 consists of transistor 119 connected to resistor memory element 118 by vias 122, 123, and 124. As shown in FIG. 1, the bitcells of the conventional memory array are formed side-by-side. The bitcells of the conventional memory array are not stackable. The density of the bitcells in the conventional memory array is limited by the size of the silicon wafer.